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| CXD2064Q Digital Comb Filter (NTSC/PAL) Description The CXD2064Q is an adaptive intra-field comb filter compatible with NTSC and PAL systems, and can provide high-precision Y/C separation with a single chip. Features * Adaptive intra-field Y/C separation * M-PAL and N-PAL supported * Vertical enhancer * Horizontal aperture correction * 8-bit A/D converter (1-channel) * 8-bit D/A converter (2-channel) * 4x PLL * Sync tip clamp * Four 1H delay lines Applications Y/C separation for color TVs and VCRs Structure Silicon gate CMOS ICStructure 48 pin QFP (Plastic) Absolute Maximum Ratings (Ta = 25C, VSS = 0V) * Supply voltage DVDD VSS - 0.5 to +7.0 V DAVD VSS - 0.5 to +7.0 V ADVD VSS - 0.5 to +7.0 V PLVD VSS - 0.5 to +7.0 V CLVD VSS - 0.5 to +7.0 V * Input voltage VI * Output voltage VO * Storage temperature Tstg VSS - 0.5 to VDD + 0.5 VSS - 0.5 to VDD + 0.5 -55 to +150 V V C Recommended Operating Conditions * Supply voltage DVDD 5.0 0.25 DAVD 5.0 0.25 ADVD 5.0 0.25 PLVD 5.0 0.25 CLVD 5.0 0.25 * Analog input ADIN 1.75 * Operating temperature Topr -20 to +70 V V V V V Vp-p C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E96X19B91-PS CXD2064Q Pin Configuration NTPL1 26 36 35 34 33 32 31 TEST 30 29 28 27 25 FIN 37 CKSL 38 PLSL 39 MCKO 40 ADCK 41 CPO 42 PLVS 43 VCV 44 PLVD 45 CLVD 46 CLPEN 47 CLVS 48 NTPL2 TEST TEST TEST APCN DVDD TRAP DVSS DVSS DVDD 24 DTR 23 PNR 22 21 VEH1 VEH2 20 VEH3 19 18 17 16 15 14 13 MOD1 DVSS MOD2 DVDD TEST VB IRF 1 2 3 4 5 6 7 8 9 10 11 12 RB RT CLPO ADVS DAVS ADVD ADIN ACO DAVD VG Block Diagram Vertical enhancement circuit ADIN 2 A/D NTSC: 1H PAL : 2H NTSC: 1H PAL : 2H DL CLPO 1 Clamp Adaptive filter operation Logical operation 4fsc D/A 9 AYO AYO VRF D/A 7 ACO Phase comparator VCO 1/4 SW 1/2 42 CPO 44 VCV 39 PLSL 37 FIN SW 38 CKSL -2- CXD2064Q Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 17 19 20 21 22 23 24 25 26 27 Symbol I/O Description Internal clamp circuit current output. Connect to ADIN when using the internal clamp. Leave this pin open when not in use. Comb filter analog input (A/D converter input). Reference bottom voltage for the A/D converter (0.52V typ.). A/D converter analog ground. A/D converter analog power supply. (5.0V) Reference top voltage for the A/D converter (2.60V typ.). Analog chroma signal output. Output can be obtained by connecting a resistor between this pin and the analog ground. D/A converter analog power supply. (5.0V) Analog luminance signal output. Output can be obtained by connecting a resistor between this pin and the analog ground. D/A converter analog ground. D/A converter related pin. Connect a capacitor of approximately 0.1F between this pin and the analog power supply (DAVD). Sets the full-scale value of the Y and C-channel D/A converter output signal. Connect a resistor of "16R" (16 times the output resistor "R" of the D/A converter). D/A converter related pin. Connect to the analog ground (DAVS) via a capacitor of approximately 0.1F. Test pin. Normally fix to "Low". Digital power supply. (5.0V) Digital ground. Y/C separation mode setting. MOD2 L H H MOD1 L L H Adaptive processing mode BPF separation mode Through mode CLPO ADIN RB ADVS ADVD RT ACO DAVD AYO DAVS VG VRF IRF VB TEST DVDD DVSS MOD2 MOD1 VEH3 VEH2 VEH1 PNR DTR NTPL2 NTPL1 DVDD O I O -- -- O O -- O -- O I O O I -- -- I I I I I I I I I -- Vertical enhancement setting. Can be set in 8 stages from VEH3 VEH2 VEH1: LLL (off) to HHH (max.) L: NTSC/H: PAL, M-PAL, N-PAL Normally fix to "Low". NTSC/PAL/M-PAL/N-PAL mode setting. NTPL2 L L H H NTPL1 L H L H NTSC PAL M-PAL N-PAL Digital power supply. (5.0V) -3- CXD2064Q Pin No. 28 29 30 31 32 33 34 35 36 37 Symbol TEST DVSS APCN TRAP TEST TEST DVDD TEST DVSS FIN I/O I -- I I I I -- I -- I Test pin. Normally fix to "Low". Digital ground. Description Horizontal aperture correction circuit setting. Low: Off, High: On. Trap filter setting. Low: Off, High: On. Test pin. Normally open or fix to "Low". Test pin. Normally open or fix to "Low". Digital power supply. (5.0V) Test pin. Normally open or fix to "Low". Digital ground. Clock input. Input the burst-locked fsc (2fsc) when using the internal PLL. Input the burst-locked 4fsc when not using the internal PLL. PLL control. Low: The internal PLL is not used. The clock (4fsc) which is input to FIN is supplied internally. High: The internal PLL is used. VCO oscillation output 4fsc clock is supplied internally. Selects the clock input to FIN. Low: fsc, High: 2fsc. When inputting 4fsc to FIN (when not using the internal PLL), this pin may be set to either "Low" or "High". Clock (4fsc) output. Clock input for A/D converter. Normally connect to MCKO. PLL phase comparator output. Leave open when not using the PLL. PLL analog ground. VCO control voltage input. Connect to PLVS when not using the PLL. PLL analog power supply. (5.0V) Clamp D/A converter analog power supply. (5.0V) Clamp circuit enable pin. Low: Clamp on, High: Clamp off. Clamp D/A converter analog ground. 38 CKSL I 39 40 41 42 43 44 45 46 47 48 PLSL MCKO ADCK CPO PLVS VCV PLVD CLVD CLPEN CLVS I O I O -- I -- -- I -- -4- CXD2064Q Electrical Characteristics DC Characteristics Item Symbol DVDD DAVD Supply voltage ADVD PLVD CLVD Operating temperature Supply current Input/output voltage Input voltage Input rise/fall time Topr IDD VI, VO VIH VIL CMOS level input -- IOH = -2mA IOH = -3mA VOL Clock input amplitude Feedback resistance value Input leak current Clock amplifier output delay 1 2 3 4 5 6 7 8 9 All pins All pins other than 6 All input pins other than 6 All output pins other than 5 CPO (Pin 42) FIN (Pin 37) All input pins other than 8 Pins 32, 33 and 35 MCKO (Pin 40) VIN RFB IIL, IIH IIH -- IOL = 4mA IOL = 1.5mA fmax = 50MHz sine wave VIN = Vss or VDD VIN = Vss or VDD VIH = VDD -- 0.5 250k -10 40 3.0 100 9.0 1M 2.5M 10 240 18.0 ns Vp-p A 0.4 0 VDD - 0.8 V -- Clock 18MHz -- -20 -- Vss 0.7VDD 0.3VDD 500 ns 90 +70 -- VDD C mA V V -- 2 3 1 4 5 4 5 6 7 8 9 -- 4.75 5.0 5.25 V 1 Measurement conditions (VDD = 4.75 to 5.25V, VSS = 0V, Ta = -20 to +70C) Min. Typ. Max. Unit Applicable pins tr, tf VOH Output voltage -5- CXD2064Q I/O Pin Capacitance (Ta = 25C, f = 1MHz, VIN = VOUT = 0V) Item Input pin capacitance Output pin capacitance Symbol CIN COUT Min. -- -- Min. -- -- Max. 9 11 Unit pF Internal 8-bit A/D Converter Characteristics (VDD = 5V, Ta = 25C, f = 10MHz) Item Resolution Max. conversion speed Analog input bandwidth Self bias Output data delay Differential linearity error Integral linearity error n fmax BW VRB VRT - VRB tpd ED EL -3dB Symbol Conditions Min. -- 18 -- 0.48 1.96 -- -1.0 -2.0 Typ. 8 -- 18 0.52 2.08 -- -- -- Max. -- -- -- 0.56 2.22 45 +1.0 +2.0 Unit bit MSPS MHz V V ns LSB LSB Internal 8-bit D/A Converter Characteristics (VDD = 5V, VRF = 2V, RIRF = 3.3k, R = 200, Ta = 25C, f = 10MHz) Item Resolution Max. conversion speed Differential linearity error Integral linearity error Output full-scale voltage Output full-scale current Output offset voltage Glitch energy n fmax ED EL VFS IFS VOS GE R = 75, 1Vp-p output Symbol Conditions Min. -- 18 -0.8 -2.0 1.805 -- -- -- Typ. 8 -- -- -- 1.90 9.5 -- 30 Max. -- -- +0.8 +2.0 1.995 15 1.0 -- Unit bit MSPS LSB LSB V mA mV pV-s Internal Clamp (VDD = 5V, Ta = 25C, f = 10MHz) Item Clamp level 1 1 Sync tip clamp Symbol CLV Conditions Min. -- Typ. 0.67 Max. -- Unit V -6- CXD2064Q Description of Functions * Y/C separation mode The Y/C separation mode can be switched by the following pin settings. Mode name Adaptive processing mode BPF separation mode Through mode MOD2 (Pin 17) L H H MOD1 (Pin 19) L L H Adaptive processing mode: Y/C separation is performed by detecting the correlation between three lines and switching between comb filter and BPF processing. BPF separation mode: Y/C separation is performed only by BPF processing. Through mode: The composite video signal input from ADIN (Pin 2) is A/D converted and then D/A converted without modification. D/A outputs are AYO (Pin 9) and ACO (Pin 7). * Horizontal aperture correction circuit This circuit corrects the frequency response degradation caused by the aperture effects accompanying D/A conversion. This circuit is valid in the adaptive processing and BPF separation modes noted above. * Trap filter circuit A trap filter is applied to remove the frequency components near fsc in the luminance signal after Y/C separation. This reduces the fsc frequency component gain by approximately 2.5dB. This circuit is valid in the adaptive processing and BPF separation modes noted above. * Using the internal PLL (clock selection method) FIN (Pin 37) fsc input PLL used PLL not used 2fsc input 4fsc input CKSL (Pin 38) H H L PLSL (Pin 39) L H L/H -7- CXD2064Q * Vertical enhancement circuit This circuit generates an enhanced component in accordance with the vertical aperture component (luminance difference from the preceding and following lines) of the luminance signal. The vertical aperture of the picture can be enhanced naturally by adding this enhanced component to the luminance signal after Y/C separation. The enhancement level can be set in eight steps. The size of | a | in the figure below varies according to the pin settings. Accordingly,enhanced level can be changed for portions of natural pictures with small luminance differences where the effects are particularly easy to see. Portions with large luminance differences are cut with a limiter so that they are not excessively enhanced. Also, portions with extremely large luminance differences such as white and black lines are not enhanced because they need be enhanced any more. Enhancement level Limiter 0 -a a Limiter Luminance difference Enhancement level OFF 1 2 3 4 5 6 Max Pin settings VEH3 (Pin 20) L L L L H H H H VEH2 (Pin 21) L L H H L L H H VEH1 (Pin 22) L H L H L H L H Small |a| -- Large -8- CXD2064Q Application Circuit for D/A Converter Block 8 10 0.1 DAVD AYO 9 3k 200 (R) Y output 10 DAVS VRF 12 2k IRF 13 3.3k (R') ACO 7 200 (R) VG 11 0.1 : Analog power Supply (5V) VB 14 0.1 : Analog ground C output 0.1 * Method of selecting the output resistor The CXD2064Q has a built-in current output type D/A converter. To obtain the output voltages, connect resistors to the AYO and ACO pins. The specs are as follows: output full-scale voltage VFS = 0.5 to 2.0 [V], output full-scale current IFS = 0 to 15 [mA]. Calculate the output resistance value using the relationship VFS = IFS x R. In addition, connect a resistor of 16 times the output resistor to the reference current pin (IRF). In case this results in a unpractical value, use a resistance value as close to the calculated value as possible. Note that, at this time, VFS = VRF x 16R/R' (VRF: Pin voltage of VRF). Here, R is the resistor connected to AYO/ACO, and R' is the resistor connected to IRF. Power consumption can be reduced by using higher resistance values, but the glitch energy and data settling time increase contrastingly. Set the optimum values according to the system applications. * VDD, VSS Separate the analog and digital systems around the device to reduce the effects of noise. DAVD is bypassed to DAVS as close to each other as possible through a ceramic capacitor of approximately 0.1F. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. -9- CXD2064Q External Connection Diagram H LH L H LH L 0.1 36 35 34 33 32 31 30 29 0.1 28 27 26 25 NTPL1 TEST TEST Clock Input 37 FIN H L H L 0.001 38 CKSL 39 PLSL NTPL2 TRAP TEST DVDD APCN TEST DVDD DVSS DVSS DTR 24 PNR 23 VEH1 22 VEH2 21 VEH3 20 MOD1 19 DVSS 18 MOD2 17 0.1 DVDD 16 TEST 15 VB 14 40 MCKO 41 ADCK 42 CPO 560 0.022 44 VCV 0.1 45 PLVD 46 CLVD 0.1 H L 47 CLPEN 56k 43 PLVS H L H L H L H L H L H L H L 0.1 3.3k ADVD DAVD CLPO ADVS ACO DAVS ADIN AYO 48 CLVS IRF 13 RB 1 2 3 4 5 6 7 8 0.1 9 VG 11 0.1 RT 10 12 0.1 Composite Video Input 10 0.1 0.1 0.1 VRF 3k 2k : Analog power Supply (5V) : Analog ground : Digital power Supply (5V) : Digital ground H : CMOS High level L : CMOS Low level 200 C output 200 Y output 0.1 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 10 - CXD2064Q Notes on Operation * Make the wiring for the signal input to ADIN (Pin 2) as short as possible. Also, drive the input signal to ADIN at low impedance. * Make the analog and digital power supply and GND lines as wide and short as possible to ensure low impedance. * Bypass the analog and digital power supply pins to GND with a ceramic capacitor of about 0.1F connected as close to the pin as possible. * Input a clock that is locked to the burst signal of the input video signal. * Separate the wiring to the clock input pin FIN (Pin 37) from the external analog circuits, analog power supplies and analog GND. * ADIN (analog input signal) Set the input signal peak-to-peak value VPP to 1.75V or less. Additionally, VPP is recommended to be 1.3V or more since the A/D converter input dynamic range should be made as large as possible. C B 2.60V (Reference top voltage typical value for internal A/D converter) VPP 0.67V (Sync tip clamp level) A 0.52V (Reference bottom voltage typical value for internal A/D converter) The DC level at the ADIN pin is as shown in the diagram above when the internal sync tip clamp is used. Labeling the internal D/A converter AYO output full-scale voltage as VFS, the correspondence between the ADIN pin voltage and AYO output pin voltage (DC level) is as follows; DC voltage at point B AYO maximum output voltage [V] DC voltage at point A 0 [V] DC voltage at point C VFS [V] The VFS is the AYO output voltage generated when the voltage equivalent to the point C is input. * Internal delay The delay from the internal A/D converter to the D/A converter output is as follows; NTSC: 1H + 24.5 clocks + ns PAL: 2H + 24.5 clocks + ns (: D/A converter analog output delay = approximately 20ns) The 24.5 clocks are the sum of the clocks shown below; A/D converter: 3.5 clocks ("0.5" is for fetching the data at the fall of the clock.) Internal logic: 20 clocks D/A converter: 1 clock - 11 - CXD2064Q Application Circuit 1 * fsc is used for clock H LH L H LH L X'tal PAL : 4.43MHz NTSC : 3.58MHz 36 0.1 35 34 33 32 31 30 29 0.1 28 27 26 25 TEST TEST TRAP TEST DVDD APCN TEST DVDD DVSS NTPL1 DVSS NTPL2 Burst-locked Clock (fsc) Clock Generator H L H L 37 FIN 0.001 38 CKSL 39 PLSL DTR 24 PNR 23 VEH1 22 VEH2 21 VEH3 20 MOD1 19 DVSS 18 MOD2 17 0.1 DVDD 16 TEST 15 VB 14 40 MCKO 41 ADCK 42 CPO 560 0.022 44 VCV 0.1 45 PLVD 46 CLVD 0.1 H L 47 CLPEN 56k 43 PLVS H L H L H L H L H L H L H L 0.1 3.3k ADVD DAVD CLPO ADVS ACO DAVS ADIN AYO 48 CLVS IRF 13 RB 1 2 3 4 5 6 7 8 0.1 9 VG 11 0.1 RT 10 12 0.1 LPF Composite Video Input 10 0.1 0.1 0.1 VRF 3k 2k 0.1 : Analog power Supply (5V) : Analog ground 200 : Digital power Supply (5V) : Digital ground H : CMOS High level L : CMOS Low level LPF 200 C output LPF Y output Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 12 - CXD2064Q Application Circuit 2 * 2fsc is used for clock H LH L H LH L X'tal PAL : 8.86MHz NTSC : 7.16MHz 36 0.1 35 34 33 32 31 30 29 0.1 28 27 26 25 TEST TEST NTPL1 TRAP TEST DVDD NTPL2 APCN TEST DVDD DVSS DVSS Burst-locked Clock (2fsc) Clock Generator H L H L 37 FIN 0.001 38 CKSL 39 PLSL DTR 24 PNR 23 VEH1 22 VEH2 21 VEH3 20 MOD1 19 DVSS 18 MOD2 17 0.1 DVDD 16 TEST 15 VB 14 40 MCKO 41 ADCK 42 CPO 560 0.022 44 VCV 0.1 45 PLVD 46 CLVD 0.1 H L 47 CLPEN 56k 43 PLVS H L H L H L H L H L H L H L 0.1 3.3k ADVD DAVD CLPO ADVS ACO DAVS ADIN AYO 48 CLVS IRF 13 RB 1 2 3 4 5 6 7 8 0.1 9 VG 11 0.1 RT 10 12 0.1 LPF Composite Video Input 10 0.1 0.1 0.1 VRF 3k 2k 0.1 : Analog power Supply (5V) : Analog ground 200 : Digital power Supply (5V) : Digital ground H : CMOS High level L : CMOS Low level LPF 200 C output LPF Y output Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 13 - CXD2064Q Application Circuit 3 * 4fsc is used for clock H LH L HLHL X'tal PAL : 17.7MHz NTSC : 14.3MHz 36 0.1 35 34 33 32 31 30 29 0.1 28 27 26 25 TEST TEST NTPL1 NTPL2 TRAP TEST DVDD APCN TEST DVDD DVSS DVSS Burst-locked Clock (4fsc) Clock Generator H L H L 37 FIN 0.001 38 CKSL 39 PLSL DTR 24 PNR 23 VEH1 22 VEH2 21 VEH3 20 MOD1 19 DVSS 18 MOD2 17 0.1 DVDD 16 TEST 15 VB 14 40 MCKO 41 ADCK 42 CPO 43 PLVS 44 VCV 0.1 45 PLVD 46 CLVD 0.1 H L 47 CLPEN H L H L H L H L H L H L H L 0.1 3.3k ADVD DAVD CLPO ADVS ACO DAVS ADIN AYO 48 CLVS IRF 13 RB 1 2 3 4 5 6 7 8 0.1 9 VG 11 0.1 RT 10 12 0.1 LPF Composite Video Input 10 0.1 0.1 0.1 VRF 3k 2k 0.1 : Analog power Supply (5V) : Analog ground 200 : Digital power Supply (5V) : Digital ground H : CMOS High level L : CMOS Low level LPF 200 C output LPF Y output Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 14 - CXD2064Q Package Outline Unit : mm 48PIN QFP (PLASTIC) 15.3 0.4 + 0.4 12.0 - 0.1 + 0.1 0.15 - 0.05 0.15 36 25 37 24 48 13 + 0.2 0.1 - 0.1 1 + 0.15 0.3 - 0.1 12 0.8 0.24 M + 0.35 2.2 - 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-48P-L04 QFP048-P-1212 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY 0.7g - 15 - 0.9 0.2 13.5 |
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